The present invention relates to electronic semiconductor devices and methods of fabrication, and more specifically, to scaled, high speed gallium arsenide bipolar transistors with reduced emitter base junction capacitance.
Semiconductor devices fabricated in gallium arsenide are preferred over devices processed in silicon for high frequency applications due to the higher mobility of carriers in gallium arsenide. Furthermore, most gallium arsenide technologies are expected to exhibit improved radiation hardness for total dose ionizing radiation. Recent advances in epitaxial technology have made possible a gallium arsenide bipolar transistor with a wide band gap emitter. Such heterostructure devices, which employ energy gap variations rather than electric fields to control the forces acting on carriers, allow optimized doping levels and device scaling which result in even higher speed devices. Further improvement in operating speed can be realized by scaling down the lateral dimensions of the transistor. Such scaling, however, is limited by the difficulty in contacting the transistor in a simple planar layout. While some attempt has been made to realize a scaled heterojunction bipolar device by using sophisticated photolithographic techniques, it appears that the greatest promise lies in the formation of a layered structure that is suitable for device scaling. Such techniques have been successfully utilized in fabricating a scaled down silicon transistor. For background, see T. Sakai, et al, Gigabit Logic Bipolar Technology: Advanced Super Self-Aligned Process Technology, Electron. Lett., Vol. 19, No. 8, pp. 283-284, Apr. 14, 1983.
The recognized advantages of GaAs buried-emitter heterojunction devices in integrated circuit form were reported by W. V. McLevige et al in GaAs/AlGaAs Heterojunction Bipolar Transistors for Integrated Circuit Applications, IEEE Electron Device Letters, Vol. EDL-3, No. 2, February 1982. More recently, the improved characteristics of this technology have been realized in the fabrication of a 4K gate array which employed heterojunction inverted transistor integrated logic (HI2L) (Yuan et al, A 4K GaAs Gate Array, 1986 ISSCC Dig. Tech. Papers 74). While these developments are impressive, the need for even higher operating speeds and greater device packing density is ever present. Clearly, improved device characteristics and packing density may be realized by scaling device geometries; however, present HI2L transistor structures, such as those reported in the above references, embody several built-in limitations that make reduction of feature size difficult. For instance, the current devices incorporate a P+ base contact region that requires excessive area to ensure ohmic contact to the base. This large area P+ region accounts for as much as one half of the emitter to base junction capacitance which reduces operating speed. In addition, present HI2L designs employ a collector region that is difficult to downsize because it must be large enough to permit a nested Schottky contact. While self-aligned processes offer some improvement, it is not expected that this technique will reduce emitter to base area by more than a factor of two to three.
Accordingly, it would be desirable to form a bipolar transistor having reduced emitter to base junction area which is capable of being scaled down without the limitation of excessive collector and base areas required for base and nested Schottky contacts.